The down-scaling of CMOS devices and the emergence of new applications have become driving forces in the evolution of Analogue-to-Digital Converter (ADC) architecture. Technology down-scaling towards nanometer devices is challenging conventional IC design methodology. In particular, the low intrinsic gain and reduced dynamic range of devices, due to low supply voltages, make it difficult to design an ADC based on voltage domain signal processing.
However, the enhanced speed, increased time resolution, and reduced size of modern nanometer devices enables highly integrated high-speed digital design, leading to the reduction of design effort. Therefore, digital dominant ADC architectures based on time domain signal processing have become a promising ADC architecture.
Emerging applications also start to require energy efficient operation of ADCs over a wide range of speeds. For example, a multi-standard receiver, a multi-sensor system, and a multi-format video processor system necessitate operation speeds ranging from KiloSample per second (KS/s) to MegaSamples per second (MS/s).
A power scalable pipelined ADC has been proposed in Imran Ahmed and David A. Johns, “A 50 MS/s (35 mW) to 1 KS/s (15 uW) power scalable 10 bit pipelined ADC using rapid power-on opamps and minimal bias current variation,” in IEEE J. Solid-State Circuits, vol. 40, no. 12, December 2005, pp. 2446-2455. This circuit operates at speeds ranging from 1 KS/s to 50 MS/s. However, this architecture is based on an analog intensive approach, namely an op-amp design.
A conventional Voltage Controlled Oscillator (VCO)-based ADC is instead a digital dominant architecture, showing potential for operation over a wide range of speeds.
An open loop VCO-based ADC was proposed in Takamoto Watanabe, Tamotsu Mizuno, and Yasuaki Makino, “An all-digital Analog-to-digital Converter with 12 uV/LSB using moving average filtering,” IEEE J. Solid-State Circuits, vol. 38, no. 1, pp. 120-125, January 2003. This ADC is based on an all-digital approach, consisting of a ring delay line, a counter, a latch, an encoder and a subtractor. Because this ADC was proposed for a sensor interface application, the design emphasis was placed on the high bit-resolution and compact size/area. The number of circulations in a ring delay line is counted for coarse quantization, and the fine phase quantization is performed by a latch and an encoder. Using this quantized information, an analog input voltage signal is converted into a digital code. However, since the same starting point in the ring delay line is used all the time, the properties of dynamic element matching (DEM) and first-order noise shaping cannot be achieved.
In order to compensate for the above disadvantages, a VCO can replace a ring delay line in the same architecture. As a result, DEM and first-order noise shaping properties can be achieved. Moreover, a variant of this architecture using differential input and passive interpolation has been developed so as to enhance the linearity and the bit resolution. This is disclosed in Jorg Daniels, Wim Dehaene, Andreas Wiesbauer, and Michiel Steyaert, “A 0.02 mm2 65 nm CMOS 30 MHz BW All-Digital differential VCO-based ADC with 64 dB SNDR,” in IEEE Symp. VLSI circuits Techn. Dig. Of Papers, pp. 155-156, June 2010
Another important consideration for a VCO-based ADC is the trade-off between speed and bit resolution. If the sampling speed gets slower, the bit resolution is improved due to the accumulation of phase information. However, in the case of moderate/high resolution VCO-based ADCs, power consumption does not change severely with respect to the sampling frequency because a VCO keeps oscillating and it is the main contributor to the overall power consumption.
There is a conventional belief that a digital dominant ADC is always power scalable with respect to the sampling frequency, even though power scalability is only guaranteed when the power-consuming operation is synchronized to the sampling clock. In a conventional VCO-based ADC, the VCO's oscillation and a portion of quantization operation occur regardless of the sampling clock. This makes the power scalability poor in a conventional VCO-based ADC.